Efficient Computer, a fabless semiconductor startup, is seeking a Test Engineer with hands-on DFT and fabless semiconductor test experience to join the Operations team. This mid-level role sits at the intersection of Hardware Engineering and Supply Chain and Operations, and you will own test engineering across active chip programs, serving as the primary interface between our engineering team and our foundry, OSAT, and test partners. You will drive test engineering across programs from DFT strategy to ATPG pattern generation and ATE bring-up through production test. What you will do: DFT Strategy and Pattern Development – define and execute DFT strategy for each chip program; generate and validate ATPG patterns including scan, MBIST, JTAG, and embedded memory read/write sequences; develop and maintain STIL and PDL for ATE execution; drive DFT sign-offs and resolve pattern-level issues with external partners. ATE Bring-up and Test Program Development – develop and debug test programs on Advantest and Teradyne platforms; execute first silicon bring-up; characterize device behavior across voltage, temperature, and frequency corners; coordinate load board bring-up and interface validation; manage test flows from wafer probe to final test and bin sort; optimize test time. OSAT and Supplier Coordination – act as the primary interface with OSAT partners and test houses; manage test program handoff and documentation; track yield data and drive corrective actions; support die traceability and OTP programming. Cross-Program Ownership – build scalable test infrastructure and documenta

Efficient Computer, a fabless semiconductor startup, is seeking a Test Engineer with hands-on DFT and fabless semiconductor test experience to join the Operations team. This mid-level role sits at the intersection of Hardware Engineering and Supply Chain and Operations, and you will own test engineering across active chip programs, serving as the primary interface between our engineering team and our foundry, OSAT, and test partners. You will drive test engineering across programs from DFT strategy to ATPG pattern generation and ATE bring-up through production test. What you will do: DFT Strategy and Pattern Development – define and execute DFT strategy for each chip program; generate and validate ATPG patterns including scan, MBIST, JTAG, and embedded memory read/write sequences; develop and maintain STIL and PDL for ATE execution; drive DFT sign-offs and resolve pattern-level issues with external partners. ATE Bring-up and Test Program Development – develop and debug test programs on Advantest and Teradyne platforms; execute first silicon bring-up; characterize device behavior across voltage, temperature, and frequency corners; coordinate load board bring-up and interface validation; manage test flows from wafer probe to final test and bin sort; optimize test time. OSAT and Supplier Coordination – act as the primary interface with OSAT partners and test houses; manage test program handoff and documentation; track yield data and drive corrective actions; support die traceability and OTP programming. Cross-Program Ownership – build scalable test infrastructure and documenta